NAND FLASH memory is electrically organized as a plurality of blocks on a die (chip), and a plurality of dies may be incorporated into a package, which may be termed a FLASH memory circuit. The chip may have more than one plane so as to be separately addressable for erase, write and read operations. A block is comprised of a plurality of pages, and the pages are comprised of a plurality of sectors. Some of this terminology is a legacy from hard disk drive (HDD) technology; however, as used in FLASH memory devices, some adaptation is made. NAND FLASH memory is characterized in that data may be written to a sector of memory, or to a contiguous group of sectors comprising a page. Pages can be written in order within a block, but if page is omitted, the present technology does not permit writing to the omitted page until the entire block has been erased. This contrasts with disk memory where a change to data in a memory location may be made by writing to that location, regardless of the previous state of the location. A block is the smallest extent of FLASH memory that can be erased, and a block must be erased prior to being written (programmed) with data.
Earlier versions of NAND FLASH had the capability of writing sequentially to sectors of a page, and data may be written on a sector basis where the die architecture permits this to be done. More recently, memory circuit manufacturers are evolving the device architecture so that one or more pages of data may be written in a write operation. This includes implementations where the die has two planes and the planes may be written simultaneously. All of this is by way of saying that the specific constraints on reading or writing data may be device dependent, but the overall approach disclosed herein may be easily adapted by a person of skill in the art so as to accommodate specific device features. The terms “erase” and “write” in a FLASH memory have the characteristic that when an erase or a write operation is in progress, a plane of the FLASH memory chip on which the operation is being performed is not available for “read” operations to any location in a plane of the chip.
One often describes stored user data by the terms sector, page, and block, but there is additional housekeeping data that is also stored and which must be accommodated in the overall memory system design. Auxiliary data such as metadata, including error correcting codes and the like that are related in some way to stored data is often said to be stored in a “spare” area. The spare area may be allocated on a sector, a page, or a block basis. Typically the organization of the data and auxiliary data follows that format of the disk memory systems due to the use of legacy user software. But, a page of a block or the block of data may be somewhat arbitrarily divided into physical memory extents that may be used for data, or for auxiliary data. So there is some flexibility in the amount of memory that is used for data and for auxiliary data in a block of data, and this is managed by some form of operating system abstraction, usually in one or more controllers associated with a memory chip, or with a module that includes the memory chip. The interface between the non-volatile memory cells and the chip bus is typically a volatile buffer memory, and the buffer memory may have a size equal to that of a data page plus the space for auxiliary data.
The management of reading of data, writing of data, and the background operations such as wear leveling and garbage collection, are performed by a system controller, using an abstraction termed a flash translation layer (FTL) that maps logical addresses (LBA), as understood by the user, to the physical addresses (PBA) of the memory where the data values are actually stored. The generic details of a FTL are known to a person of skill in the art and are not described in detail herein. The use of a FTL or equivalent is assumed, and the discussion herein takes the view that the abstraction of the FTL is equivalent of mapping the logical address of a page of user data to a physical memory location. The location may be a page of a physical memory block. This is not intended to be a limitation, but such an assumption simplifies the discussion.
SCSI compatible disk drives may be reformatted to 520-byte sectors, yielding 8 extra bytes per sector. These 8 bytes have traditionally been used by RAID controllers to store internal protection information. The T10-DIF (Data Integrity Field) is an extension to the SCSI Block Commands that standardizes the format of the 8 extra bytes associated with each 512 byte user sector and defines ways to interact with the contents at the protocol level.
Each 8-byte DIF tuple is split into three chunks:                a 16-bit guard tag containing a CRC of the data portion of the sector;        a 16-bit application tag; and,        a 32-bit reference tag which contains an incrementing counter for each sector.        
The T10-DIF format has been standardized, so both initiators and targets (as well as potentially transport switches in-between) are able to verify the integrity of the data. When writing, the host bus adapter (HBA) may DMA (direct memory access) transfer 512-byte sectors from a host memory, generate the matching integrity metadata and send out 520-byte sectors to the storage device. The disk controller will verify the integrity of the data before committing it to non-volatile storage. When reading the data, the disk controller will send 520-byte sectors to the HBA. The HBA will verify the data integrity and DMA 512-byte sectors to host memory. Since current generation software products are usually designed to be used with rotating media storage systems, a FLASH memory system, while not subject to many of the constraints of a mechanical disk system, is nevertheless constrained to be at least compatible with the existing software architectures.